8 projects

Aditus: door access from a phone or a watch

A Flutter and Wear OS access-control prototype, with per-device RSA keys, Bluetooth authentication, an ESP32 controller and a Flask backend.

FlutterDartPythonFlaskSQLAlchemySQLiteC++ESP32Wear OSBLE

An FPGA IoT gateway with a custom AES core

From a VHDL AES-128 core to live sensor readings: a Nexys A7 gateway with bare-metal C firmware, Ethernet telemetry, and a Python controller.

VHDLCPythonFPGAVivadoAXI4-Lite

Mining DETI coins across CPUs and GPUs

A C and CUDA performance project exploring SIMD, OpenMP, GPU search, and a TCP collector, with measurements from the original experiments.

CCUDAOpenMPAVX2AVX-512WebAssembly

A moving average, built in hardware

Inside a VHDL signal filter: the four-sample datapath, ROM handshake, reset controllers, and simulation checks on a DE2-115 FPGA.

VHDLFPGAQuartusModelSimPython